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-rw-r--r--.gitignore11
-rw-r--r--firmware/Makefile97
-rw-r--r--firmware/buspirate.cfg35
-rwxr-xr-xfirmware/makedev.sh1
-rw-r--r--firmware/openocd.cfg34
-rw-r--r--firmware/src/dac.c24
-rw-r--r--firmware/src/dac.h7
-rw-r--r--firmware/src/p2m.c126
-rw-r--r--firmware/src/sample.h1108
-rw-r--r--firmware/src/uart.c169
-rw-r--r--firmware/src/uart.h50
11 files changed, 1662 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..0fd2f37
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,11 @@
+toolchain/arm-toolchain
+toolchain/build
+toolchain/src
+toolchain/tarballs
+*.o
+*.d
+*.bin
+*.hex
+*.elf
+*.map
+*.dump \ No newline at end of file
diff --git a/firmware/Makefile b/firmware/Makefile
new file mode 100644
index 0000000..ef9b0e1
--- /dev/null
+++ b/firmware/Makefile
@@ -0,0 +1,97 @@
+#/* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+# * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+# * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+# * THE AUTHORS SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+# * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. USE IT AT YOUR OWN RISK */
+
+ARCH = arm-none-eabi
+top_srcdir=${PWD}
+LPC=${top_srcdir}/lpc17xx
+DRV=${top_srcdir}/drivers
+SRC=${top_srcdir}/src
+
+PROJ=p2m
+EXECNAME=$(PROJ).elf
+
+# Tool definitions
+CC = $(ARCH)-gcc
+LD = $(ARCH)-ld
+AR = $(ARCH)-ar
+AS = $(ARCH)-as
+CP = $(ARCH)-objcopy
+OD = $(ARCH)-objdump
+SIZE = $(ARCH)-size
+RM = rm
+Q = # @./quiet "$@"
+
+# Flags
+CFLAGS = -W -Wall -O0 --std=gnu99 -fgnu89-inline -mcpu=cortex-m3 -mthumb
+CFLAGS += -ffunction-sections -fdata-sections
+CFLAGS += -I${LPC} -I${DRV}
+ASFLAGS =
+LDFLAGS = --gc-sections
+
+STDLIB_LDFLAGS =
+#STDLIB_LDFLAGS += -L/home/deva/lib/arm/arm-toolchain/lib/gcc/arm-none-eabi/4.6.2/
+#STDLIB_LDFLAGS += -L/home/deva/lib/arm/arm-toolchain/arm-none-eabi/lib/
+#STDLIB_LDFLAGS += -lc -lgcc
+
+CPFLAGS =
+ODFLAGS = -x --syms
+PRFLAGS ?=
+
+# Source files
+LINKER_SCRIPT = ${LPC}/LPC17xx.ld
+CSRCS = \
+ ${LPC}/startup_LPC17xx.c \
+ $(wildcard ${CMSIS}/*.c) \
+ $(wildcard ${LPC}/*.c) \
+ $(wildcard ${DRV}/*.c) \
+ $(wildcard ${SRC}/*.c)
+CSRCS += ${SRC}/${PROJ}.c
+ASRCS =
+
+
+OBJS = $(CSRCS:.c=.o) $(ASRCS:.s=.o)
+
+.PHONY: all size clean nuke
+
+all: ${PROJ}.bin ${PROJ}.hex
+
+size: ${PROJ}.elf
+ @$(SIZE) $<
+
+%.hex: %.elf
+ $Q $(CP) $(CPFLAGS) -O ihex $< $*.hex
+
+%.bin: %.elf
+ $Q $(CP) $(CPFLAGS) -O binary $< $*.bin
+
+${PROJ}.elf: $(LINKER_SCRIPT) $(OBJS)
+ $Q $(LD) -Map $(@:.elf=.map) $(LDFLAGS) -T $^ -o $@ $(STDLIB_LDFLAGS)
+ $Q $(OD) $(ODFLAGS) $@ > $(@:.elf=.dump)
+ @$(SIZE) $@
+
+%.o: %.c
+ @$(CC) -MM $< -MF $*.d -MP
+ $Q $(CC) -c $(CFLAGS) $< -o $@
+
+%.o: %.S
+ $Q $(AS) $(ASFLAGS) $< -o $@
+
+clean:
+ @-$(RM) -f *.elf
+ @-\
+for D in "." "**"; do \
+ $(RM) -f $$D/*.o $$D/*.d $$D/*.lst $$D/*.dump $$D/*.map; \
+done
+
+nuke: clean
+ -$(RM) -f *.hex *.bin
+
+.PHONY : flash
+flash: $(EXECNAME)
+ $(CP) -O ihex $(EXECNAME) $(PROJ).hex
+ openocd -f openocd.cfg -c 'flash write_image erase $(PROJ).hex' -c 'verify_image $(PROJ).hex' -c 'reset run'
+
+-include $(CSRCS:.c=.d)
diff --git a/firmware/buspirate.cfg b/firmware/buspirate.cfg
new file mode 100644
index 0000000..8d85846
--- /dev/null
+++ b/firmware/buspirate.cfg
@@ -0,0 +1,35 @@
+# =========================================================
+# What: BusPirate Version 3b with OpenOCD support
+# Using: USB serial on COM port 13
+# JTAG: <available pins & description>
+# See: http://dangerousprototypes.com/docs/Bus_Pirate_JTAG_connections_for_OpenOCD
+# Note: 1) If you have "normal" mode AND "0" pullup,
+# THEN do not connect Vpu & VTref!
+# 2) Cygwin uses serial USB COM ports as:
+# /dev/ttyS[N-1] == /dev/comN
+# Make sure it's not already used with
+# any other terminal or programs...
+# =========================================================
+interface buspirate
+# Not yet implemented properly...
+#transport select jtag
+# Set the serial port to be used:
+buspirate_port /dev/buspirate
+#buspirate_port /dev/ttyS12
+# Set "normal" or "fast" (~1 MHz)communication speed:
+buspirate_speed normal
+# Turn OFF the voltage regulator:
+#buspirate_vreg 0
+# ---------------------------------------------------------
+# Remember that VTref (Vcc) is connected to pull-up's.
+# If you are NOT using pull-up's with "normal" drain
+# pin-mode, then do NOT connect Vpu to VTref!
+# ---------------------------------------------------------
+buspirate_mode normal
+buspirate_pullup 0
+# ---------------------------------------------------------
+#buspirate_mode open-drain
+#buspirate_pullup 1
+# ---------------------------------------------------------
+# This depends on the cable, you are safe with this option:
+reset_config srst_only \ No newline at end of file
diff --git a/firmware/makedev.sh b/firmware/makedev.sh
new file mode 100755
index 0000000..fc69fb2
--- /dev/null
+++ b/firmware/makedev.sh
@@ -0,0 +1 @@
+cd /dev; ln -s ttyUSB0 buspirate; ln -s ttyUSB1 ftdi
diff --git a/firmware/openocd.cfg b/firmware/openocd.cfg
new file mode 100644
index 0000000..44bdfb3
--- /dev/null
+++ b/firmware/openocd.cfg
@@ -0,0 +1,34 @@
+# This file is for use with the PhotonSaw LPC1769 based laserctrl board.
+# The script will flash the main.bin file to the board and run it.
+# To flash the board call with:
+# $ openocd -f openocd-flash.cfg
+
+jtag_khz 1
+
+# This is the JTAG connector I use
+#source [find interface/olimex-arm-usb-tiny-h.cfg]
+source [find interface/buspirate.cfg]
+
+# This is close enough to the board I use
+source [find target/lpc1768.cfg]
+
+adapter_nsrst_assert_width 10
+adapter_nsrst_delay 2
+reset_config srst_only
+
+#adapter_khz 0
+adapter_khz 500
+#jtag_khz 100
+
+init
+sleep 200
+reset halt
+#sleep 200
+#soft_reset_halt
+wait_halt
+mww 0x400FC040 0x01
+sleep 200
+
+#flash write_image erase vcomdemo.hex
+#verify_image vcomdemo.hex
+#reset runq
diff --git a/firmware/src/dac.c b/firmware/src/dac.c
new file mode 100644
index 0000000..2773f00
--- /dev/null
+++ b/firmware/src/dac.c
@@ -0,0 +1,24 @@
+#include "dac.h"
+
+//#include "api.h"
+#include <LPC17xx.h>
+
+void dac_init()
+{
+ // setup the related pin to DAC output
+ LPC_PINCON->PINSEL1 = 0x00200000; // set p0.26 to DAC output
+
+ // Clock tick pr. sample delay (DAC clock)
+ LPC_DAC->DACCNTVAL = 2267; // 44111Hz
+ LPC_DAC->DACCTRL = (0x1<<1)|(0x1<<2);
+ LPC_SC->PCLKSEL0 |= (0x1 << 22); // Use full 100MHz clock
+}
+
+#define VOL 1
+void dac_play_samples(const short int *samples, int size)
+{
+ for(int i = 0; i < size; i++) {
+ LPC_DAC->DACR = ((unsigned short)(samples[i] * VOL)<< 6);// | DAC_BIAS;
+ for(int j = 0; j < 100; j++) { if(!LPC_DAC->DACR) LPC_DAC->DACR = 0; }
+ }
+}
diff --git a/firmware/src/dac.h b/firmware/src/dac.h
new file mode 100644
index 0000000..6ee34bc
--- /dev/null
+++ b/firmware/src/dac.h
@@ -0,0 +1,7 @@
+#ifndef __DAC_H__
+#define __DAC_H__
+
+void dac_init();
+void dac_play_samples(const short int *samples, int size);
+
+#endif/*__DAC_H__*/
diff --git a/firmware/src/p2m.c b/firmware/src/p2m.c
new file mode 100644
index 0000000..422cd34
--- /dev/null
+++ b/firmware/src/p2m.c
@@ -0,0 +1,126 @@
+/* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * THE AUTHORS SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. USE IT AT YOUR OWN RISK */
+
+#include <LPC17xx.h>
+
+#define SPI
+
+#ifdef DMA
+
+#include "dac.h"
+#include "sample.h"
+
+int main (void)
+{
+ dac_init();
+
+ // int i = 0;
+ while(1) {
+ // fiprintf(stderr, "Play #%d: %d samples\n\r", i++, sizeof(samples) / sizeof(short));
+ dac_play_samples(samples, sizeof(samples) / sizeof(short));
+ }
+ return 0;
+}
+
+#endif
+volatile uint32_t temp;
+
+void _delay(uint32_t del);
+
+#ifdef BLINKY
+
+int main (void)
+{
+ LPC_SC->PCONP |= ( 1 << 15 ); // power up GPIO
+ LPC_GPIO1->FIODIR |= 1 << 29; // puts P1.29 into output mode.
+ while(1)
+ {
+ LPC_GPIO1->FIOPIN |= 1 << 29; // make P1.29 high
+ _delay( 1 << 24 );
+ LPC_GPIO1->FIOPIN &= ~( 1 << 29 ); // make P1.29 low
+ _delay( 1 << 24 );
+ }
+ return 0;
+
+}
+
+#endif
+
+#ifdef UART
+
+#include "LPC17xx.h"
+#include <stdint.h>
+#include "uart.h"
+
+int main (void)
+{
+ /* SystemClockUpdate() updates the SystemFrequency variable */
+ // SystemCoreClockUpdate();//SystemClockUpdate();
+ UARTInit(0, 115200); /* baud rate setting */
+ // UARTInit(1, 8000); /* baud rate setting */
+
+ LPC_SC->PCONP |= ( 1 << 15 ); // power up GPIO
+ LPC_GPIO1->FIODIR |= 1 << 29; // puts P1.29 into output mode.
+
+ while (1) {
+ LPC_GPIO1->FIOPIN |= 1 << 29; // make P1.29 high
+
+ //LPC_UART0->IER = IER_THRE | IER_RLS; // Disable RBR
+ UARTSend(0, (uint8_t *)"hello\n\r", 7);
+ //LPC_UART0->IER = IER_THRE | IER_RLS | IER_RBR; // Re-enable RBR
+
+ _delay( 1 << 22 );
+
+ ///
+
+ LPC_GPIO1->FIOPIN &= ~( 1 << 29 ); // make P1.29 low
+ /*
+ LPC_UART0->IER = IER_THRE | IER_RLS; // Disable RBR
+ UARTSend( 0, (uint8_t *)"l", 1);
+ LPC_UART0->IER = IER_THRE | IER_RLS | IER_RBR; // Re-enable RBR
+ */
+ _delay( 1 << 22 );
+
+ }
+}
+
+#endif
+
+#ifdef SPI
+
+#include "LPC17xx.h"
+#include <stdint.h>
+#include "uart.h"
+
+int main (void)
+{
+ UARTInit(0, 115200); /* baud rate setting */
+
+ UARTSend(0, (uint8_t *)"init\n\r", 6);
+
+ // PCONP register (Table 46), set bit PCSPI.
+ LPC_SC->PCONP |= 1 << 8;
+
+ // In the PCLKSEL0 register (Table 40), set bit PCLK_SPI. In master mode, the
+ // clock must be an even number greater than or equal to 8
+ LPC_SC->PCLKSEL0PCLK_SPI = 0;//(3 << 17);
+ // 1Mhz
+
+ while (1) {
+ UARTSend(0, (uint8_t *)"hello\n\r", 7);
+
+ _delay( 1 << 22 );
+ }
+}
+
+#endif
+
+void _delay(uint32_t del)
+{
+ uint32_t i;
+ for(i=0;i<del;i++)
+ temp = i;
+}
diff --git a/firmware/src/sample.h b/firmware/src/sample.h
new file mode 100644
index 0000000..8ac9f46
--- /dev/null
+++ b/firmware/src/sample.h
@@ -0,0 +1,1108 @@
+/*
+ * Num samples: 1097
+ * Max: 10554
+ * Min: -10171
+ * Offset-Korr-Max: 20725
+ * Offset-Korr-Min: 0
+ * Scale: 0.049409
+ * Scaled-Max: 1024
+ */
+short samples[] = {
+ 489,
+ 697,
+ 791,
+ 758,
+ 703,
+ 611,
+ 536,
+ 395,
+ 232,
+ 284,
+ 539,
+ 711,
+ 739,
+ 658,
+ 536,
+ 476,
+ 444,
+ 367,
+ 346,
+ 408,
+ 394,
+ 330,
+ 368,
+ 423,
+ 385,
+ 437,
+ 625,
+ 673,
+ 542,
+ 457,
+ 419,
+ 360,
+ 369,
+ 430,
+ 421,
+ 398,
+ 447,
+ 460,
+ 381,
+ 335,
+ 350,
+ 365,
+ 416,
+ 462,
+ 449,
+ 434,
+ 393,
+ 303,
+ 249,
+ 269,
+ 324,
+ 387,
+ 406,
+ 327,
+ 203,
+ 164,
+ 247,
+ 357,
+ 379,
+ 306,
+ 263,
+ 339,
+ 372,
+ 267,
+ 210,
+ 227,
+ 215,
+ 206,
+ 224,
+ 258,
+ 325,
+ 352,
+ 269,
+ 223,
+ 288,
+ 279,
+ 188,
+ 135,
+ 106,
+ 129,
+ 206,
+ 229,
+ 211,
+ 239,
+ 250,
+ 194,
+ 195,
+ 255,
+ 284,
+ 262,
+ 222,
+ 260,
+ 267,
+ 146,
+ 145,
+ 253,
+ 264,
+ 273,
+ 282,
+ 224,
+ 213,
+ 246,
+ 227,
+ 146,
+ 85,
+ 89,
+ 122,
+ 140,
+ 175,
+ 219,
+ 243,
+ 201,
+ 113,
+ 121,
+ 180,
+ 106,
+ 50,
+ 61,
+ 104,
+ 172,
+ 242,
+ 270,
+ 226,
+ 163,
+ 111,
+ 70,
+ 48,
+ 65,
+ 69,
+ 43,
+ 56,
+ 50,
+ 19,
+ 7,
+ 0,
+ 11,
+ 105,
+ 197,
+ 154,
+ 78,
+ 52,
+ 35,
+ 74,
+ 169,
+ 181,
+ 120,
+ 145,
+ 208,
+ 190,
+ 158,
+ 126,
+ 72,
+ 51,
+ 37,
+ 19,
+ 22,
+ 48,
+ 72,
+ 145,
+ 215,
+ 168,
+ 124,
+ 146,
+ 110,
+ 63,
+ 80,
+ 103,
+ 83,
+ 85,
+ 99,
+ 133,
+ 217,
+ 218,
+ 156,
+ 201,
+ 260,
+ 229,
+ 209,
+ 239,
+ 225,
+ 173,
+ 163,
+ 212,
+ 296,
+ 370,
+ 381,
+ 341,
+ 320,
+ 323,
+ 300,
+ 247,
+ 226,
+ 263,
+ 286,
+ 236,
+ 207,
+ 288,
+ 383,
+ 398,
+ 380,
+ 354,
+ 309,
+ 332,
+ 417,
+ 422,
+ 363,
+ 326,
+ 312,
+ 332,
+ 382,
+ 448,
+ 520,
+ 545,
+ 510,
+ 486,
+ 505,
+ 527,
+ 554,
+ 592,
+ 586,
+ 530,
+ 500,
+ 518,
+ 535,
+ 535,
+ 566,
+ 628,
+ 648,
+ 603,
+ 566,
+ 567,
+ 572,
+ 585,
+ 619,
+ 657,
+ 698,
+ 718,
+ 696,
+ 688,
+ 698,
+ 704,
+ 717,
+ 706,
+ 681,
+ 677,
+ 668,
+ 682,
+ 721,
+ 713,
+ 667,
+ 651,
+ 688,
+ 724,
+ 709,
+ 686,
+ 674,
+ 647,
+ 671,
+ 745,
+ 763,
+ 744,
+ 743,
+ 756,
+ 761,
+ 745,
+ 755,
+ 802,
+ 833,
+ 862,
+ 885,
+ 877,
+ 887,
+ 917,
+ 908,
+ 867,
+ 839,
+ 831,
+ 843,
+ 841,
+ 799,
+ 784,
+ 815,
+ 826,
+ 825,
+ 860,
+ 888,
+ 887,
+ 882,
+ 893,
+ 912,
+ 903,
+ 878,
+ 878,
+ 896,
+ 885,
+ 876,
+ 913,
+ 962,
+ 997,
+ 1006,
+ 980,
+ 953,
+ 922,
+ 869,
+ 844,
+ 884,
+ 939,
+ 965,
+ 978,
+ 997,
+ 1008,
+ 988,
+ 950,
+ 913,
+ 898,
+ 910,
+ 937,
+ 966,
+ 964,
+ 916,
+ 886,
+ 923,
+ 961,
+ 946,
+ 937,
+ 956,
+ 953,
+ 961,
+ 993,
+ 1017,
+ 1024,
+ 1002,
+ 949,
+ 902,
+ 904,
+ 937,
+ 944,
+ 926,
+ 955,
+ 1005,
+ 1014,
+ 991,
+ 976,
+ 967,
+ 939,
+ 898,
+ 900,
+ 930,
+ 938,
+ 926,
+ 895,
+ 863,
+ 888,
+ 946,
+ 969,
+ 954,
+ 920,
+ 888,
+ 901,
+ 931,
+ 896,
+ 851,
+ 851,
+ 845,
+ 844,
+ 869,
+ 889,
+ 905,
+ 924,
+ 909,
+ 872,
+ 862,
+ 867,
+ 849,
+ 825,
+ 831,
+ 879,
+ 915,
+ 889,
+ 874,
+ 890,
+ 895,
+ 898,
+ 886,
+ 839,
+ 813,
+ 834,
+ 852,
+ 817,
+ 764,
+ 745,
+ 756,
+ 760,
+ 757,
+ 779,
+ 819,
+ 823,
+ 802,
+ 811,
+ 841,
+ 837,
+ 805,
+ 776,
+ 753,
+ 753,
+ 793,
+ 817,
+ 777,
+ 728,
+ 718,
+ 745,
+ 783,
+ 783,
+ 742,
+ 706,
+ 719,
+ 769,
+ 794,
+ 782,
+ 775,
+ 762,
+ 732,
+ 717,
+ 715,
+ 705,
+ 683,
+ 673,
+ 687,
+ 704,
+ 704,
+ 694,
+ 668,
+ 634,
+ 629,
+ 644,
+ 647,
+ 652,
+ 653,
+ 620,
+ 624,
+ 676,
+ 670,
+ 639,
+ 655,
+ 679,
+ 688,
+ 686,
+ 665,
+ 633,
+ 606,
+ 595,
+ 603,
+ 607,
+ 572,
+ 533,
+ 527,
+ 542,
+ 591,
+ 629,
+ 591,
+ 550,
+ 537,
+ 528,
+ 546,
+ 572,
+ 561,
+ 540,
+ 538,
+ 541,
+ 538,
+ 539,
+ 537,
+ 553,
+ 581,
+ 574,
+ 535,
+ 518,
+ 520,
+ 514,
+ 508,
+ 511,
+ 528,
+ 558,
+ 566,
+ 552,
+ 548,
+ 530,
+ 492,
+ 483,
+ 507,
+ 511,
+ 489,
+ 471,
+ 467,
+ 469,
+ 489,
+ 498,
+ 458,
+ 420,
+ 414,
+ 405,
+ 422,
+ 467,
+ 485,
+ 471,
+ 444,
+ 430,
+ 449,
+ 478,
+ 491,
+ 484,
+ 461,
+ 435,
+ 412,
+ 401,
+ 404,
+ 395,
+ 389,
+ 404,
+ 394,
+ 368,
+ 367,
+ 373,
+ 375,
+ 375,
+ 395,
+ 423,
+ 421,
+ 412,
+ 417,
+ 400,
+ 371,
+ 371,
+ 377,
+ 356,
+ 334,
+ 363,
+ 409,
+ 399,
+ 361,
+ 353,
+ 361,
+ 378,
+ 406,
+ 419,
+ 424,
+ 417,
+ 395,
+ 368,
+ 338,
+ 326,
+ 339,
+ 343,
+ 330,
+ 341,
+ 366,
+ 362,
+ 351,
+ 374,
+ 400,
+ 385,
+ 349,
+ 335,
+ 338,
+ 337,
+ 328,
+ 332,
+ 359,
+ 359,
+ 327,
+ 313,
+ 316,
+ 329,
+ 347,
+ 351,
+ 337,
+ 333,
+ 351,
+ 365,
+ 353,
+ 344,
+ 357,
+ 363,
+ 344,
+ 334,
+ 344,
+ 350,
+ 344,
+ 342,
+ 335,
+ 333,
+ 332,
+ 329,
+ 353,
+ 387,
+ 389,
+ 375,
+ 381,
+ 395,
+ 388,
+ 376,
+ 373,
+ 368,
+ 358,
+ 356,
+ 359,
+ 370,
+ 389,
+ 407,
+ 420,
+ 420,
+ 407,
+ 405,
+ 415,
+ 423,
+ 426,
+ 407,
+ 374,
+ 369,
+ 380,
+ 384,
+ 389,
+ 396,
+ 397,
+ 405,
+ 406,
+ 378,
+ 371,
+ 395,
+ 402,
+ 401,
+ 397,
+ 397,
+ 408,
+ 400,
+ 386,
+ 388,
+ 391,
+ 404,
+ 432,
+ 451,
+ 457,
+ 457,
+ 448,
+ 435,
+ 435,
+ 437,
+ 448,
+ 475,
+ 487,
+ 481,
+ 476,
+ 467,
+ 448,
+ 436,
+ 428,
+ 417,
+ 433,
+ 465,
+ 470,
+ 476,
+ 493,
+ 495,
+ 489,
+ 472,
+ 446,
+ 438,
+ 446,
+ 451,
+ 453,
+ 457,
+ 468,
+ 489,
+ 500,
+ 490,
+ 486,
+ 494,
+ 505,
+ 511,
+ 499,
+ 485,
+ 490,
+ 491,
+ 487,
+ 492,
+ 501,
+ 505,
+ 514,
+ 517,
+ 504,
+ 488,
+ 495,
+ 521,
+ 533,
+ 533,
+ 526,
+ 511,
+ 509,
+ 513,
+ 506,
+ 499,
+ 498,
+ 512,
+ 542,
+ 553,
+ 544,
+ 535,
+ 529,
+ 528,
+ 534,
+ 538,
+ 545,
+ 559,
+ 557,
+ 536,
+ 524,
+ 523,
+ 529,
+ 539,
+ 545,
+ 551,
+ 561,
+ 554,
+ 528,
+ 514,
+ 516,
+ 519,
+ 522,
+ 534,
+ 548,
+ 559,
+ 554,
+ 533,
+ 521,
+ 526,
+ 526,
+ 518,
+ 526,
+ 547,
+ 556,
+ 556,
+ 564,
+ 567,
+ 557,
+ 549,
+ 552,
+ 562,
+ 570,
+ 564,
+ 548,
+ 539,
+ 542,
+ 551,
+ 552,
+ 545,
+ 543,
+ 550,
+ 560,
+ 574,
+ 582,
+ 570,
+ 552,
+ 544,
+ 532,
+ 525,
+ 536,
+ 554,
+ 563,
+ 552,
+ 536,
+ 540,
+ 549,
+ 551,
+ 552,
+ 544,
+ 532,
+ 532,
+ 543,
+ 551,
+ 558,
+ 559,
+ 547,
+ 533,
+ 527,
+ 525,
+ 526,
+ 527,
+ 522,
+ 512,
+ 497,
+ 496,
+ 507,
+ 507,
+ 496,
+ 490,
+ 486,
+ 478,
+ 470,
+ 471,
+ 481,
+ 489,
+ 494,
+ 490,
+ 478,
+ 473,
+ 480,
+ 486,
+ 488,
+ 492,
+ 492,
+ 489,
+ 482,
+ 473,
+ 465,
+ 460,
+ 451,
+ 438,
+ 431,
+ 434,
+ 436,
+ 430,
+ 418,
+ 412,
+ 421,
+ 436,
+ 439,
+ 428,
+ 417,
+ 408,
+ 399,
+ 392,
+ 393,
+ 406,
+ 420,
+ 422,
+ 413,
+ 400,
+ 388,
+ 381,
+ 379,
+ 375,
+ 372,
+ 375,
+ 382,
+ 388,
+ 384,
+ 380,
+ 388,
+ 392,
+ 387,
+ 381,
+ 377,
+ 380,
+ 386,
+ 379,
+ 363,
+ 350,
+ 340,
+ 334,
+ 336,
+ 340,
+ 345,
+ 351,
+ 355,
+ 359,
+ 361,
+ 350,
+ 334,
+ 326,
+ 324,
+ 320,
+ 315,
+ 313,
+ 308,
+ 304,
+ 306,
+ 309,
+ 311,
+ 312,
+ 312,
+ 313,
+ 306,
+ 297,
+ 297,
+ 302,
+ 295,
+ 283,
+ 279,
+ 286,
+ 299,
+ 308,
+ 307,
+ 304,
+ 300,
+ 292,
+ 283,
+ 275,
+ 276,
+ 284,
+ 281,
+ 269,
+ 269,
+ 276,
+ 275,
+ 275,
+ 285,
+ 291,
+ 288,
+ 284,
+ 279,
+ 268,
+ 256,
+ 252,
+ 259,
+ 259,
+ 249,
+ 242,
+ 243,
+ 250,
+ 259,
+ 260,
+ 250,
+ 236,
+ 227,
+ 222,
+ 226,
+ 238,
+ 247,
+ 244,
+ 236,
+ 230,
+ 228,
+ 226,
+ 226,
+ 228,
+ 229,
+ 232,
+ 239,
+ 247,
+ 251,
+ 253,
+ 253,
+ 252,
+ 251,
+ 247,
+ 241,
+ 239,
+ 238,
+ 235,
+ 233,
+ 230,
+ 229,
+ 231,
+ 230,
+ 228,
+ 230,
+ 235,
+ 246,
+ 254,
+ 251,
+ 245,
+ 239,
+ 233,
+ 227,
+ 226,
+ 231,
+ 239,
+ 247,
+ 252,
+ 250,
+ 242,
+ 232,
+ 227,
+ 229,
+ 230,
+ 227,
+ 227,
+ 231,
+ 239,
+ 248,
+ 243,
+ 226,
+ 222,
+ 232,
+ 236,
+ 235,
+ 238,
+ 244,
+ 246,
+ 243,
+ 240,
+ 240,
+ 243,
+ 240,
+ 241,
+ 251,
+ 258,
+ 259,
+ 255,
+ 244,
+ 234,
+ 233,
+ 239,
+ 245,
+ 252,
+ 254,
+ 250,
+ 251,
+ 255,
+ 252,
+ 247,
+ 249,
+ 253,
+ 253,
+ 255,
+ 260,
+ 264,
+ 266,
+ 267,
+ 265,
+ 264,
+ 268,
+ 273,
+ 277,
+ 280,
+ 281,
+ 281,
+ 283,
+ 284,
+ 279,
+ 280,
+ 286,
+ 290,
+ 290,
+ 291,
+ 291,
+ 288,
+ 288,
+ 287,
+ 286,
+ 288,
+ 289,
+ 291,
+ 300,
+ 309,
+ 314,
+ 321,
+ 323,
+ 318,
+ 320,
+ 325,
+ 328,
+ 332,
+ 336,
+ 340,
+ 346,
+ 355,
+ 359,
+ 355,
+ 353,
+ 358,
+ 364,
+ 369,
+ 375,
+ 379,
+ 373,
+ 368,
+ 369,
+ 375,
+ 383,
+ 394,
+ 402,
+ 405,
+ 405,
+ 405,
+ 402,
+ 401,
+ 406,
+ 413,
+ 415,
+ 408,
+ 407,
+ 421,
+ 435,
+ 439,
+ 438,
+ 440,
+ 443,
+ 451,
+ 465,
+ 472,
+ 473,
+ 471,
+ 470,
+ 477,
+ 486,
+ 485
+};
diff --git a/firmware/src/uart.c b/firmware/src/uart.c
new file mode 100644
index 0000000..d3ac789
--- /dev/null
+++ b/firmware/src/uart.c
@@ -0,0 +1,169 @@
+/****************************************************************************
+ * $Id:: uart.c 5751 2010-11-30 23:56:11Z usb00423 $
+ * Project: NXP LPC17xx UART example
+ *
+ * Description:
+ * This file contains UART code example which include UART initialization,
+ * UART interrupt handler, and APIs for UART access.
+ *
+ ****************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+****************************************************************************/
+#include <LPC17xx.h>
+#include <stdint.h>//"type.h"
+#include "uart.h"
+
+#define TRUE 1
+#define FALSE 0
+
+volatile uint32_t UART0Status, UART1Status;
+volatile uint8_t UART0TxEmpty = 1, UART1TxEmpty = 1;
+
+/*****************************************************************************
+** Function name: UARTInit
+**
+** Descriptions: Initialize UART port, setup pin select,
+** clock, parity, stop bits, FIFO, etc.
+**
+** parameters: portNum(0 or 1) and UART baudrate
+** Returned value: true or false, return false only if the
+** interrupt handler can't be installed to the
+** VIC table
+**
+*****************************************************************************/
+uint32_t UARTInit( uint32_t PortNum, uint32_t baudrate )
+{
+ uint32_t Fdiv;
+ uint32_t pclkdiv, pclk;
+
+ uint32_t SystemFrequency = SystemCoreClock;
+
+ if ( PortNum == 0 )
+ {
+ LPC_PINCON->PINSEL0 &= ~0x000000F0;
+ LPC_PINCON->PINSEL0 |= 0x00000050; /* RxD0 is P0.3 and TxD0 is P0.2 */
+ /* By default, the PCLKSELx value is zero, thus, the PCLK for
+ all the peripherals is 1/4 of the SystemFrequency. */
+ /* Bit 6~7 is for UART0 */
+ pclkdiv = (LPC_SC->PCLKSEL0 >> 6) & 0x03;
+ switch ( pclkdiv )
+ {
+ case 0x00:
+ default:
+ pclk = SystemFrequency/4;
+ break;
+ case 0x01:
+ pclk = SystemFrequency;
+ break;
+ case 0x02:
+ pclk = SystemFrequency/2;
+ break;
+ case 0x03:
+ pclk = SystemFrequency/8;
+ break;
+ }
+
+ LPC_UART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
+ Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
+ LPC_UART0->DLM = Fdiv / 256;
+ LPC_UART0->DLL = Fdiv % 256;
+ LPC_UART0->LCR = 0x03; /* DLAB = 0 */
+ LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
+
+ // NVIC_EnableIRQ(UART0_IRQn);
+
+ //LPC_UART0->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART0 interrupt */
+ return (TRUE);
+ }
+ else if ( PortNum == 1 )
+ {
+ LPC_PINCON->PINSEL4 &= ~0x0000000F;
+ LPC_PINCON->PINSEL4 |= 0x0000000A; /* Enable RxD1 P2.1, TxD1 P2.0 */
+
+ /* By default, the PCLKSELx value is zero, thus, the PCLK for
+ all the peripherals is 1/4 of the SystemFrequency. */
+ /* Bit 8,9 are for UART1 */
+ pclkdiv = (LPC_SC->PCLKSEL0 >> 8) & 0x03;
+ switch ( pclkdiv )
+ {
+ case 0x00:
+ default:
+ pclk = SystemFrequency/4;
+ break;
+ case 0x01:
+ pclk = SystemFrequency;
+ break;
+ case 0x02:
+ pclk = SystemFrequency/2;
+ break;
+ case 0x03:
+ pclk = SystemFrequency/8;
+ break;
+ }
+
+ LPC_UART1->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
+ Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
+ LPC_UART1->DLM = Fdiv / 256;
+ LPC_UART1->DLL = Fdiv % 256;
+ LPC_UART1->LCR = 0x03; /* DLAB = 0 */
+ LPC_UART1->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
+
+ // NVIC_EnableIRQ(UART1_IRQn);
+
+ LPC_UART1->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART1 interrupt */
+ return (TRUE);
+ }
+ return( FALSE );
+}
+
+/*****************************************************************************
+** Function name: UARTSend
+**
+** Descriptions: Send a block of data to the UART 0 port based
+** on the data length
+**
+** parameters: portNum, buffer pointer, and data length
+** Returned value: None
+**
+*****************************************************************************/
+void UARTSend( uint32_t portNum, uint8_t *BufferPtr, uint32_t Length )
+{
+ if ( portNum == 0 )
+ {
+ while ( Length != 0 )
+ {
+ /* THRE status, contain valid data */
+ //while ( !(UART0TxEmpty & 0x01) );
+ LPC_UART0->THR = *BufferPtr;
+ UART0TxEmpty = 0; /* not empty in the THR until it shifts out */
+ BufferPtr++;
+ Length--;
+ }
+ }
+ else
+ {
+ while ( Length != 0 )
+ {
+ /* THRE status, contain valid data */
+ while ( !(UART1TxEmpty & 0x01) );
+ LPC_UART1->THR = *BufferPtr;
+ UART1TxEmpty = 0; /* not empty in the THR until it shifts out */
+ BufferPtr++;
+ Length--;
+ }
+ }
+ return;
+}
+
+/******************************************************************************
+** End Of File
+******************************************************************************/
diff --git a/firmware/src/uart.h b/firmware/src/uart.h
new file mode 100644
index 0000000..870f581
--- /dev/null
+++ b/firmware/src/uart.h
@@ -0,0 +1,50 @@
+/****************************************************************************
+ * $Id:: uart.h 5751 2010-11-30 23:56:11Z usb00423 $
+ * Project: NXP LPC17xx UART example
+ *
+ * Description:
+ * This file contains UART code header definition.
+ *
+ ****************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+****************************************************************************/
+#ifndef __UART_H
+#define __UART_H
+
+#define IER_RBR 0x01
+#define IER_THRE 0x02
+#define IER_RLS 0x04
+
+#define IIR_PEND 0x01
+#define IIR_RLS 0x03
+#define IIR_RDA 0x02
+#define IIR_CTI 0x06
+#define IIR_THRE 0x01
+
+#define LSR_RDR 0x01
+#define LSR_OE 0x02
+#define LSR_PE 0x04
+#define LSR_FE 0x08
+#define LSR_BI 0x10
+#define LSR_THRE 0x20
+#define LSR_TEMT 0x40
+#define LSR_RXFE 0x80
+
+#define BUFSIZE 0x40
+
+uint32_t UARTInit( uint32_t portNum, uint32_t Baudrate );
+void UARTSend(uint32_t portNum, uint8_t *BufferPtr, uint32_t Length );
+
+#endif /* end __UART_H */
+/*****************************************************************************
+** End Of File
+******************************************************************************/
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 17:53:56 +0000