diff options
Diffstat (limited to 'firmware/drivers/i2s.h')
| -rw-r--r-- | firmware/drivers/i2s.h | 43 |
1 files changed, 30 insertions, 13 deletions
diff --git a/firmware/drivers/i2s.h b/firmware/drivers/i2s.h index 6a8d446..1cbac51 100644 --- a/firmware/drivers/i2s.h +++ b/firmware/drivers/i2s.h @@ -85,39 +85,47 @@ typedef enum { * Sets DAO register values and stops/resets the bus. * @param ww Word width of pcm values. * @param ch Number of channels (mono/stereo) + * @param ws_halfperiod The width of a word select period in bitclock ticks + * divided by two. */ -void i2s_set_dao_register(i2s_wordwidth_t ww, i2s_channels_t ch); +void i2s_set_dao_register(i2s_wordwidth_t ww, i2s_channels_t ch, + int ws_halfperiod); /** * Sets DAI register values and stops/resets the bus. * @param ww Word width of pcm values. * @param ch Number of channels (mono/stereo) + * @param ws_halfperiod The width of a word select period in bitclock ticks + * divided by two. */ -void i2s_set_dai_register(i2s_wordwidth_t ww, i2s_channels_t ch); +void i2s_set_dai_register(i2s_wordwidth_t ww, i2s_channels_t ch, + int ws_halfperiod); /** * Set clock transmit rate as PCLK_I2S * (X/Y) / 2 - * @param y_div I²S transmit MCLK rate denominator. This value is used to - * divide PCLK to produce the transmit MCLK. Eight bits of fractional divide - * supports a wide range of possibilities. A value of 0 stops the clock. * @param x_div I²S transmit MCLK rate numerator. This value is used to * multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. * Eight bits of fractional divide supports a wide range of possibilities. + * @param y_div I²S transmit MCLK rate denominator. This value is used to + * divide PCLK to produce the transmit MCLK. Eight bits of fractional divide + * supports a wide range of possibilities. A value of 0 stops the clock. * Note: the resulting ratio X/Y is divided by 2. + * Note: y must be greater than or equal to x. */ -void i2s_set_tx_rate(uint8_t y_div, uint8_t x_div); +void i2s_set_tx_rate(uint8_t x_div, uint8_t y_div); /** * Set clock receive rate as PCLK_I2S * (X/Y) / 2 - * @param y_div I²S receive MCLK rate denominator. This value is used to divide - * PCLK to produce the receive MCLK. Eight bits of fractional divide supports - * a wide range of possibilities. A value of 0 stops the clock. * @param x_div I²S receive MCLK rate numerator. This value is used to multiply * PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight * bits of fractional divide supports a wide range of possibilities. + * @param y_div I²S receive MCLK rate denominator. This value is used to divide + * PCLK to produce the receive MCLK. Eight bits of fractional divide supports + * a wide range of possibilities. A value of 0 stops the clock. * Note: the resulting ratio X/Y is divided by 2. + * Note: y must be greater than or equal to x. */ -void i2s_set_rx_rate(uint8_t y_div, uint8_t x_div); +void i2s_set_rx_rate(uint8_t x_div, uint8_t y_div); /** * I²S transmit bit rate. @@ -153,11 +161,11 @@ typedef enum { */ void i2s_set_rx_mode_control(i2s_rx_clksel_t c, int _4pin, int mcena); -void i2s_tx_reset(); +void i2s_tx_reset_fifo(); void i2s_tx_stop(); void i2s_tx_start(); -void i2s_rx_reset(); +void i2s_rx_reset_fifo(); void i2s_rx_stop(); void i2s_rx_start(); @@ -264,8 +272,17 @@ int i2s_get_state_rx_level(); */ int i2s_get_state_tx_level(); +/** + * Calculate and initialise clk values based on samplerate, channel number and + * number of bits per sample. + * @param fs The samplerate in Hz. + * @param bw The bitwidth, ie. number of bits pr. sample. + * @param ch The number of channels. + * @return 0 on success, 1 on error. + */ +int i2s_clkcalc_init(int fs, int bw, int ch); -#if 0 +#if 1 #define I2S_DMA_ENABLED 1 |